搜索资源列表
HA
- Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
Accumulator_ADD_SUB_8bit
- Adder/Subtractor for 8-bit (with full interface with FPGA board and pin assignment)
EDA1
- 完成一位二进制全减器的设计，采用文本输入法分别实现，分层设计，底层采用半加器和逻辑门实现。-Completion of a binary full subtracter design, implementation, respectively, using the text input method, hierarchical design, are based on half adder and logic gates.
subber
- 完成一位二进制全减器的设计，采用原理图输入法和文本输入法分别实现，分层设计，底层由半加器（也用原理图输入法）和逻辑门组成-Completion of a binary full subtracter design, the use of schematic and text input method input method were realized, hierarchical design, the bottom of the half adder (also used schematic
jiafaqixiuding
- 带显示界面的加法器，含有纠错功能，字体带有颜色，功能齐全-Adder with a display interface, with error correction, with the font color, full-featured
bjq
- 基于FPGA的半加器，完整工程及代码，已测试-FPGA-based half-adder, full engineering and code
1999-2387
- Vhdl study for Adder (Full / Half)
PART5
- Wallace multiplier using VHDL. THis code is constructed using full adders and half adder circuits.
full_add_8bits
- a full adder in vhdl language
module demultiplexer1
- Verilog code for demultiplexer
mux_with multiplier
- mux to use with adder with full adder and half adder
exp01_adc32
- 通过4位加法器实现32位加法器，使用串行进位的方式首先设计一个8位全加器，然后在8位全加器的基础上设计实现32位全加器(A 32 bit adder is implemented through a 4 bit adder. First, a 8 bit full adder is designed using serial carry. Then, a 32 bit full adder is designed on the basis of 8 bit full adder.)
1位加法器
- 一位全加器的功能，原理图，代码，还有一些基本使用的应用，让一位全加器能正常运行。(Function and application of a full adder)
4位全加器 计数器等程序
- EDA仿真工具使用的，进行EDA开发的多个程序； 包括：4位全加器，12分频，128分频，篮球计数秒表（部分），计数器； 可以搭配EDA仿真软件使用，也可以搭配开发板使用；(EDA simulation tools used for EDA development of multiple programs; Including: 4 bit full adder, 12 frequency division, 128 frequency division, basketball cou
quanjiaqi
- 程序的功能是在quartus II环境下实现全加器的功能。(The function of the program is to implement the full adder function in Quartus II environment.)
Inception_V3(Transfer)
- 本算法实现了InceptionV3模型的迁移学习。训练好的inceptionV3模型可自行搜索下载.pb文件，数据集需为本地jpg图片。(Realization of full adder schematic diagram)